One-Time Programmable (OTP) memory is a memory that can be programmed once and only once. An OTP can be programmed from low to high resistance states, the so-called fuse, such as electrical fuse. Alternatively, an OTP can be programmed from high to low resistance states, the so-called anti-fuse. The programming means can apply a high voltage to an OTP element such as in anti-fuse. Alternatively, the programming means can apply a high current to flow through an OTP element such as in fuse. The OTP memory cell usually has a program selector coupled to an OTP element to switch the desirable OTP element to conduct a high current or high voltage applied.
An electrical fuse is a common OTP that can be constructed from a segment of interconnect, such as polysilicon, silicided polysilicon, silicide, metal, metal alloy, or some combination thereof. The metal can be aluminum, copper, other transition metals, or the non-aluminum metal gate for CMOS. One of the most commonly used electrical fuses is a CMOS gate, fabricated in silicided polysilicon, used as interconnect. The electrical fuse can also be one or more contacts or vias instead of a segment of interconnect. A high current may blow the contact(s) or via(s) into a very high resistance state. The OTP element can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher. The anti-fuse can consist of one or more contacts or vias with an insulator in between. The anti-fuse can also be a CMOS gate coupled to a CMOS body with a thin gate oxide as insulator.
A conventional OTP memory cell is shown in FIG. 1. The cell 10 consists of an OTP element 11 and an NMOS program selector 12. The OTP element 11 is coupled to the drain of the NMOS 12 at one end, and to a positive voltage V+ at the other end. The gate of the NMOS 12 is coupled to a select signal (Sel), and the source is coupled to a negative voltage V−. When a high voltage is applied to V+ and a low voltage to V−, the OTP device 10 can be programmed by raising the select signal (Sel) to turn on the NMOS 12. One of the most common OTP elements is a silicided polysilicon, the same material and fabricated at the same time as a MOS gate. The size of the NMOS 12, as program selector, needs to be large enough to deliver the required program current for a few microseconds. The program current for a silicided polysilicon is normally between a few milliamps for a fuse with width of 40 nm to about 20 mA for a fuse with width about 0.6 um. As a result, the cell size of an electrical fuse using silicided polysilicon tends to be very large. The OTP cells 10 are usually organized as a two-dimensional array with all V+'s in the same columns coupled together as bitlines (BLs) and all Sel's in the same row coupled together as wordlines (WLs).
Another OTP memory cell 15 is shown in FIG. 1(b). The OTP memory cell has an OTP element 16 and a diode 17 as program selector. The OTP element 16 is coupled between an anode of the diode 17 and a high voltage V+. A cathode of the diode 17 is coupled to a low voltage V−. By applying a proper voltage between V+ and V− for a proper duration of time, the OTP element 16 can be programmed into high or low resistance states, depending on voltage/current and duration. The diode 17 can be a junction diode constructed from a P+ active region on N well and an N+ active region on the same N well as the P and N terminals of a diode, respectively. In another embodiment, the diode 17 can be a diode constructed from a polysilicon structure with two ends implanted by P+ and N+, respectively. The P or N terminal of either junction diode or polysilicon diode can be implanted by the same source or drain implant in CMOS devices. Either the junction diode or polysilicon diode can be built in standard CMOS processes without any additional masks or process steps. The OTP cells 15 can be organized as a two-dimensional array with all V+'s in the same columns coupled together as bitlines (BLs) and all Sel's in the same rows coupled together as wordline bars (WLBs).
Low density OTP memory (e.g. bit count no more than 256) can be used for chip ID, inventory control, parameter trimming, or configuration settings for SoC integration. Since the low density OTP size is very small, it is imperative having low pin count to further saving the overall size. To reduce pin count, the interface is better to be serial to save many address signals. The addresses are usually incremented or decremented automatically from a starting address after each access cycle.
FIG. 2(a) shows a block diagram of a typical 4-bit counter 20 that has T-type flip-flops 21-24 (TFF1-4), AND gates 25 and 26 coupled between TFF2-TFF3 and TFF3-TFF4, respectively. FIG. 2(b) shows a schematic 30 of a typical T flip-flop constructed from a D flip-flop 31 with an XOR 32. FIG. 3 shows a schematic of a typical D flip-flop 35 in almost any textbooks on CMOS circuit design. The DFF 35 is implemented as two stages of latches 36 and 37 gated by clocks with opposite phases. The total transistor count of the typical DFF in FIG. 3 is 24, or called 24T. An additional XOR (4T) and an AND gate (6T) are needed to construct a counter stage in FIGS. 2(a),(b) for a total of 34T, except that the first two counter stages can be simplified.
For a low density OTP, as small as 8-bit to 256-bit, designing the peripheral circuits needs to be very effective; otherwise the overhead would be very high. The counter and flip-flop according to the conventional designs are very ineffective. Hence, there is a need for an invention to achieve highly effective design for a low density OTP.